Date: Sat, 7 Sep 2013 11:47:49 +0200 From: Katja Malvoni <kmalvoni@...il.com> To: john-dev@...ts.openwall.com Subject: Re: ZedBoard / Parallella: bcrypt Hello, I have implementation of bcrypt's most costly loop and behavioral simulation gives correct results. But when I put it in user part of IP core generated by Create and import peripheral wizard it produces incorrect result (code is attached, user_logic.v). And I can't figure out why. If I write something to block RAM from PL, host reads correct data. If I don't modify the contents of memory, host reads the same unmodified data. If PL reads data from one location in block RAM and writes to another one, host reads expected value. My guess was that there is a problem with reading/writing to block RAM from PL but when there is no computation implemented in logic but only reads and writes it works as expected. Does anyone have an idea how to debug this? Changing portions of code to see what would happen isn't practical because bitstream generation takes 20 minutes. Current implementation is attached (bcrypt_loop.v) and it's too slow - 7652913 clock cycles for cost 5. It comes mainly from memory latency. 3 cycles are needed for a read from memory. And I can use only one port because the other one is used by DMA. When I used Create and import peripheral wizard to generate IP core, I chose AXI interface. From this guide: http://www.xilinx.com/support/documentation/ip_documentation/axi_ref_guide/latest/ug761_axi_reference_guide.pdfI got impression that there is some memory I can use and it comes as a part of the IP. I need to read the user guide more carefully to figure out how to use AXI interface and experiment with that memory. Katja Content of type "text/html" skipped Download attachment "bcrypt_loop.v" of type "application/octet-stream" (7710 bytes)
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