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Date: Mon, 26 Aug 2013 23:40:47 +0200
From: Katja Malvoni <>
Subject: Katja's weekly report #11


1. Cause of second reliability issue determined
2. It is possible to replace bitstream on Parallella board
3. Non tested verilog implementation of bcrypt's most costly loop
4. Copying S box from ARM core to block RAM seems to work (I'd need to
disable cache to be sure that it works or read it from PL and do something
with it)

1. Fix reliability issue for bcrypt on Epiphany - waiting for Yaniv's
2. Use DMA for S box transfer and implement other way of communication
(from PL to PS)
3. Integrate most costly loop with communication

Best regards,


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