Date: Mon, 26 Aug 2013 11:43:15 +0200 From: Sylvain Munaut <246tnt@...il.com> To: Solar Designer <solar@...nwall.com> Cc: john-dev@...ts.openwall.com Subject: Re: FPGA reprogramming on ZedBoard / Parallella board Hi, > One thing that doesn't work is Parallella's matmul example (new, > recently revised for the new eSDK). It just waits after "GO". That's really strange ... all the epiphany comm is done via memory map so if some epiphany code works, that means memory map access works, so it should pretty much all work .. Might be worth reporting on the forum. Cheers, Sylvai
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