Follow @Openwall on Twitter for new release announcements and other news
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Mon, 26 Aug 2013 11:43:15 +0200
From: Sylvain Munaut <>
To: Solar Designer <>
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board


> One thing that doesn't work is Parallella's matmul example (new,
> recently revised for the new eSDK).  It just waits after "GO".

That's really strange ... all the epiphany comm is done via memory map
so if some epiphany code works, that means memory map access works, so
it should pretty much all work ..

Might be worth reporting on the forum.



Powered by blists - more mailing lists

Confused about mailing lists and their use? Read about mailing lists on Wikipedia and check out these guidelines on proper formatting of your messages.