john-dev - Re: FPGA reprogramming on ZedBoard / Parallella board

Follow @Openwall on Twitter for new release announcements and other news

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Tue, 6 Aug 2013 20:40:19 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board

Hi Alexander,

I created bitstream but I'm not sure whether I generated .bin file from it
correctly. I wanted to check before replacing bitstream on board because
this task is not urgent and if I did it wrong, board won't be available for
others.
I created bitstream following those instructions:
http://www.adapteva.com/white-papers/parallella-platform-reference-design/
I deleted io_clock_gen.xco from sources and added it again. When adding it
again, it's name changed to clk_wiz_v3_6_0. After that bitstream generation
succeeded.

I used http://www.xilinx.com/support/answers/46913.html and
http://www.adapteva.com/white-papers/building-linux-for-parallella-platform/#commentsto
create .bin file from .bit file

My image looks like this:
the_ROM_image:
{
    [bootloader]zynq_fsbl_0.elf
    top_parallella16_prototype.bit
    parallella16_prototype_uboot.elf
}

For ISE 14.6 command bootgen -image <bootimage>.bif -split bin -o i
BOOT.BIN doesn't work - it fails when parsing arguments, split and bin
aren't listed in help. I used bootgen -image <bootimage>.bif -o i BOOT.BIN

Thanks,

Katja

Content of type "text/html" skipped

Confused about mailing lists and their use? Read about mailing lists on Wikipedia and check out these guidelines on proper formatting of your messages.