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Date: Tue, 6 Aug 2013 20:40:19 +0200
From: Katja Malvoni <>
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board

Hi Alexander,

I created bitstream but I'm not sure whether I generated .bin file from it
correctly. I wanted to check before replacing bitstream on board because
this task is not urgent and if I did it wrong, board won't be available for
I created bitstream following those instructions:
I deleted io_clock_gen.xco from sources and added it again. When adding it
again, it's name changed to clk_wiz_v3_6_0. After that bitstream generation

I used and
create .bin file from .bit file

My image looks like this:

For ISE 14.6 command bootgen -image <bootimage>.bif -split bin -o i
BOOT.BIN doesn't work - it fails when parsing arguments, split and bin
aren't listed in help. I used bootgen -image <bootimage>.bif -o i BOOT.BIN



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