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Date: Tue, 16 Jul 2013 21:20:39 +0200
From: Dániel Bali <>
Subject: Re: Daniel's weekly report #4

Hello Alexander!

2013/7/16 Solar Designer <>

> Daniel,
> Hmm, isn't this actually report #5, not #4?

Oops, sorry about that.

> On Mon, Jul 15, 2013 at 03:04:54PM +0200, D?niel Bali wrote:
> > 5. ISA files generated by OpenCL are now correctly translated into
> > microcode! Tested this on the raw-md4 and raw-md5 kernels.
> How did you test?  Can you perhaps post a sequence of shell commands and
> their output (for one of these kernels)?

I manually cut the microcode part from the ELF that is created when john
runs and used a python script to check for equality.

gcnasm/run/gcnasm md5_kernel.isa output.bin
python output.bin md5.bin

The script looks like this:

import binascii
import sys

if len(sys.argv) < 3:
    print "Usage: %s <input 1> <input 2>" % (sys.argv[0])

orig = open(sys.argv[1], 'rb').read()
data = open(sys.argv[2], 'rb').read()

if len(orig) != len(data):

for i in range(0, len(orig), 4):
    d1 = binascii.hexlify(orig[i:i+4][::-1])
    d2 = binascii.hexlify(data[i:i+4][::-1])
    if d1 != d2:
        print "%d: %s != %s" % (i, d2, d1)

python output.bin

> > (There were a
> > few compare instructions that needed to be tweaked to work (6-8 lines))
> Why did they need to be tweaked?  Was it a bug in ISA files generated by
> OpenCL or in your gcnasm, or something else?

The problem comes from the VOPC format. VOPC instructions can also be
represented with the VOP3b format. OpenCL's generated ISA files always use
it with VOP3b from what I've seen. However, VOP3b's operands are SDST,
VDST, SRC0, SRC1 and SRC2. The VOPC instructions in the ISA files look like

v_cmp_eq_i32  s[6:7], v5, 0

But after looking at the microcode I saw that they really mean this:

v_cmp_eq_i32  s[6:7], s0, v5, 0

This is what had to be changed. There are other inconsitencies like this in
the DS format. We would need a more flexible parser to detect these.


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