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Date: Tue, 21 May 2013 23:17:02 +0200
From: magnum <>
To: "" <>
Subject: 5x intrinsics?

I see Alain's NT format is "5x" for 32-bit SSE2 builds, ie. it does 4x in SSE2 plus 1x in non-SSE. I presume these are interleaved for hiding latency so doing that extra 1x more or less for free. Would this be theoretically and practically worthwhile for the intrinsics? Maybe it'd just get very messy. I can't remember any discussion on this matter. Perhaps the 64-bit CPU's SSE2 registers are not actually separate from the GP ones? I'm not good at these things but I guess that could be the reason this is only done in 32-bit code.


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