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Date: Fri, 22 Apr 2011 01:12:02 +0530
From: Sandeep Manchella <>
Subject: GSoC : Bcrypt Implementation on FPGA(status)


I would like to report on the status of the qualification task. The code is

I finished the code and I am still checking the functionality(I got *some
warnings* due to latch development which result in timing delay and wrong
output also sometimes, so trying to fix those) .I based* my
implementation*on the blowfish vhdl code you mentioned in the mailing
list. I obviously
used the same method for init state, P array and S boxes. The control logic
takes care of the expand-key function and encryption in ECB mode as
different states based on simple muxes.

As of now I am trying to make the code free of warnings so that it can be
properly synthesized without any timing delays. If I can complete this in
the next few hours I will post it on  or mail you
with the screenshots.

Thanking You,

P.S : It took me time to understand the blowfish implementation as I newly
learnt vhdl (around 25 days back) and I did my best :) .

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