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Date: Wed, 13 Apr 2011 09:49:35 -0300
From: Yuri Gonzaga <>
Subject: Re: Answering and asking some of the first questions

Hi, there!

I am here today to report the qualification task status, as you asked me

The task was divide in 3 main subtask:

   1. bcrypt implementation in HDL
   2. Hardware-side interface
   3. JtR-side interface

Below, each one is discussed in some details:

1. I have started to implement the bcrypt using SystemVerilog language and
Altera's Quartus II design software. The ExpandKey of EksBlowFish is almost
done, including SBoxes initialization, F function and the 18 rounds. Then, I
will get into the setup stage and, later, finish the bcrypt.

2. I am thinking of use the JTAG port avaiable in the development boards to
receive the input parameters and send back the result. This a serial port
that connects to a USB port on the Computer. Maybe, David has any suggestion
to this part.

3. I have downloaded the JtR source code. In the "c3_fmt.c" file, there is a
function named "crypt_all()", which looks like to be the right point where I
will change the code to communicate to the hardware implementation. Input
parameters are the strings "saved_key[index]" and "saved_salt", and output
result is the string "crypt_out[index]". Based in the article, where is the
third input parameter, "cost"?
There is an API to access the JTAG communication port inside the C code. So,
I will pass the parameters through the JTAG port, the FPGA will calculate
the hash and send it back to the computer. Finally, I will receive that in
the JtR using the API I mentioned.

This is my general idea. What do you think? Any recommendation?

We need to see some working code from you before we accept you for the
> project under GSoC, which we must decide on soon.

How do I can present the working code to you?

Best regards,

Yuri Gonzaga Gonçalves da Costa
Master's Candidate in Informatics
Digital System Laboratory
Federal University of Paraíba - Brazil

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