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Date: Wed, 30 Sep 2015 18:55:58 +0300
From: Aleksey Cherepanov <lyosha@...nwall.com>
To: john-dev@...ts.openwall.com
Subject: Re: Re: ztex 1.15y boards, pre-development

Katja,

On Mon, Sep 28, 2015 at 02:39:45PM +0300, Aleksey Cherepanov wrote:
> On Sun, Sep 27, 2015 at 10:41:21PM +0300, Aleksey Cherepanov wrote:
> > On Mon, Jul 27, 2015 at 03:03:34AM +0300, Aleksey Cherepanov wrote:
> > > I think, I got how to bypass it: read 5 times and skip results from
> > > first 4 times. Also there is a difference: with wrong data I got 32
> > > bytes back, while good data come in 34 bytes "packet".
> > 
> > I found why there is additional word that causes 34 bytes instead of
> > 32: you check cnt >= 16 while you need cnt >= 15 because you already
> > read 16 words at cnt == 15.
> 
> I played a bit and made a slightly different bitstream: it reads only
> once and writes back only once too. The code is in attach.

I made correct code to read, copy, write back.

Speed is about 50kb/s one way. Speed may be improved by factor 8
packing data together to fill whole usb packet. Maybe it is needed to
utilize internal buffer of usb controller fully to make it work
faster. PKTEND should be disabled then.

There are no more glitches in my test runs but the code was obtained
by small (random) modifications, so I am not sure that they align with
documentation and do not fail under other circumstances. Particularly
I did not test multi chip usage.

New code is attached.

> There are problems:
> 
> - first time after power cycle it gives zeros, I use workaround: I
> upload bitstream twice, then it works correctly even for the first run
> of transfer_data

I guess that's because I thought that PKTEND is active-high, but it
turned out to be active-low (active when set to 0) by default. I guess
it might send packets with disconnected FD or with FD full of zeros,
hence zeros in the first run.

http://www.cypress.com/knowledge-base-article/function-pktend-pin
"By default, PKTEND pin is active-low; its polarity can be changed via
the FIFOPINPOLAR register"

> - I tried to make reads to return without data after the first one,
> but it is not stable: sometimes I get "got 0 bytes back" (desired),
> but sometimes it sticks with error "Error reading data: No error".

I guess "got 0 bytes back" occurs when PKTEND is active but FD is not
connected, or something like that. Now it always returns error, I
think that's ok.

> I think you messed up work with SLOE, SLRD, SLWR and PKTEND control
> signals. I found a document that describes them:
> 
> http://www.cypress.com/file/4455144551
> 
> "SLRD pin should be asserted by the master to read data from the FIFO."
> "SLWR pin should be asserted by the master to write data to the FIFO."
> "SLOE: This is the enable signal for the FIFO's output driver."
> "FIFOADR[1:0] These signals select the active endpoint."

A bit more:
http://www.cypress.com/knowledge-base-article/timing-specification-between-sloe-and-slrd-ez-usb-fx2
[...] tOEN (SLOE Turn-on to FIFO Data Valid) [...]
[...] tXFD (SLRD to FIFO Data Output Propagation Delay) [...]

I've got idea about stabilization of FIFOADR from the following code.
I like use of case statement to construct sequence of actions and make
delays.
http://svn.tapr.org/repos_sdr_hpsdr/trunk/AE6VK/EP2_LED/Verilog/EP2_LED.v

But I used your "flipper" with fr_or_sec too, because reading screwed
the first word without it. Writing works well without delays, I don't
know if it is correct and when it can break.

BTW there is a lib for easier fifo from designer of the boards:
http://opencores.org/project,ezusb_io
http://opencores.org/websvn,filedetails?repname=ezusb_io&path=%2Fezusb_io%2Ftrunk%2Fezusb_io.v

Thanks!

-- 
Regards,
Aleksey Cherepanov

// from ztex-experimental by Katja Malvoni
/* modified; may be broken; see thread: http://openwall.com/lists/john-dev/2015/07/26/2 */

module intraffic (
	input        RESET,
	input        CS,
	input        RW,
	input        IFCLK,
	input        FLAGB,
	input        FLAGC,
	inout [15:0] FD,
	output       SLOE,
	output       SLRD,
	output       SLWR,
	output       FIFOADR0,
	output       FIFOADR1,
	output       PKTEND
);

reg [255:0] data;
reg [255:0] data_out;

reg SLOE_R, SLRD_R, SLWR_R, PKTEND_R;
reg [15:0] FD_R;
reg fr_or_sec;

   reg    FIFOADR1_R;

   reg [4:0]      state;
   reg [9:0]      count;
   reg            FD_reg_connected;

assign SLOE = (CS == 1'b1) ? SLOE_R : 1'bZ;
assign SLRD = (CS == 1'b1) ? SLRD_R : 1'bZ;
assign SLWR = (CS == 1'b1) ? SLWR_R : 1'bZ;
assign FIFOADR0 = (CS == 1'b1) ? 1'b0 : 1'bZ;
// assign FIFOADR1 = (CS == 1'b1) ? ((RW == 1'b1) ? 1'b0 : 1'b1) : 1'bZ;
assign FIFOADR1 = (CS == 1'b1) ? FIFOADR1_R : 1'bZ;
assign PKTEND = (CS == 1'b1) ? PKTEND_R : 1'bZ;

assign FD = (CS == 1'b1 && FD_reg_connected == 1) ? FD_R : 16'bZ;

always @(posedge IFCLK)
begin

   if (RESET == 1) begin

      SLRD_R <= 1;
      SLOE_R <= 1;
      SLWR_R <= 1;
      PKTEND_R <= 1;
      FIFOADR1_R <= 1;

   end else begin

      case (state)

        0: begin
           // Select host->fpga EP
           FD_reg_connected <= 0;
           FIFOADR1_R <= 1;
           count <= 0;
           state <= state + 1;
           fr_or_sec <= 0;
        end

        // Wait 2 IFCLK for FIFOADR1_R to stabilize
        2: begin
           // If got data
           if (FLAGC == 1) begin
              state <= state + 1;
              // assert SLOE
              SLOE_R <= 0;
           end
           // or stick here to wait for data
        end
        // Wait 2 IFCLK before we assert SLRD

        4: begin
           if (RW == 0 && FLAGC == 1) begin
              if (fr_or_sec == 0) begin
                 data[255:16] <= data[239:0];
                 data[15:0] <= FD;
                 SLOE_R <= 1;
                 SLRD_R <= 1;
                 fr_or_sec <= 1;
              end else begin
                 data[15:0] <= FD;
                 count <= count + 1;
                 SLRD_R <= 0;
                 SLOE_R <= 0;
                 if (count == 15) begin
                    state <= state + 1;
                 end
                 fr_or_sec <= 0;
              end
           end else begin
              SLOE_R <= 1;
              SLRD_R <= 1;
           end
        end

        5: begin
           // Reset SLRD and SLOE
           SLRD_R <= 1;
           SLOE_R <= 1;
           state <= state + 1;
           count <= 0;
        end

        6: begin
           // Do work here
           // data_out <= 256'hd1310ba698dfb5ac2ffd72dbd01adfb7b8e1afed6a267e96ba7c9045f12c7f99;
           // data_out <= 256'h3400111122223333444455556666777788889999aaaabbbbccccddddeeeeffff;
           data_out <= data;
           count <= 0;
           state <= state + 1;
        end

        7: begin
           // Select fpga->host EP
           FD_reg_connected <= 1;
           FIFOADR1_R <= 0;
           count <= 0;
           state <= state + 1;
        end
        // Skip 1 tick to stabilize FIFOADR1_R

        9: begin
           // If got room
           if (FLAGB == 1) begin
              FD_R <= data_out[255:240];
              data_out[255:16] <= data_out[239:0];
              count <= count + 1;
              SLWR_R <= 0;
              if (count == 15) begin
                 state <= state + 1;
                 PKTEND_R <= 0;
              end else begin
                 PKTEND_R <= 1;
              end
           end else begin
              SLWR_R <= 1;
           end
        end

        10: begin
           // Reset SLWR
           SLWR_R <= 1;
           PKTEND_R <= 1;
           // Back to reading
           state <= 0;
        end

        default:
          state <= state + 1;

      endcase

   end

end

endmodule

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