// from ztex-experimental by Katja Malvoni
/* modified; may be broken; see thread: http://openwall.com/lists/john-dev/2015/07/26/2 */

module intraffic (
	input        RESET,
	input        CS,
	input        RW,
	input        IFCLK,
	input        FLAGB,
	input        FLAGC,
	inout [15:0] FD,
	output       SLOE,
	output       SLRD,
	output       SLWR,
	output       FIFOADR0,
	output       FIFOADR1,
	output       PKTEND
);

reg [255:0] data;
reg [255:0] data_out;

reg SLOE_R, SLRD_R, SLWR_R, PKTEND_R;
reg [15:0] FD_R;
reg fr_or_sec;

   reg    FIFOADR1_R;

   reg [4:0]      state;
   reg [9:0]      count;
   reg            FD_reg_connected;

assign SLOE = (CS == 1'b1) ? SLOE_R : 1'bZ;
assign SLRD = (CS == 1'b1) ? SLRD_R : 1'bZ;
assign SLWR = (CS == 1'b1) ? SLWR_R : 1'bZ;
assign FIFOADR0 = (CS == 1'b1) ? 1'b0 : 1'bZ;
// assign FIFOADR1 = (CS == 1'b1) ? ((RW == 1'b1) ? 1'b0 : 1'b1) : 1'bZ;
assign FIFOADR1 = (CS == 1'b1) ? FIFOADR1_R : 1'bZ;
assign PKTEND = (CS == 1'b1) ? PKTEND_R : 1'bZ;

assign FD = (CS == 1'b1 && FD_reg_connected == 1) ? FD_R : 16'bZ;

always @(posedge IFCLK)
begin

   if (RESET == 1) begin

      SLRD_R <= 1;
      SLOE_R <= 1;
      SLWR_R <= 1;
      PKTEND_R <= 1;
      FIFOADR1_R <= 1;

   end else begin

      case (state)

        0: begin
           // Select host->fpga EP
           FD_reg_connected <= 0;
           FIFOADR1_R <= 1;
           count <= 0;
           state <= state + 1;
           fr_or_sec <= 0;
        end

        // Wait 2 IFCLK for FIFOADR1_R to stabilize
        2: begin
           // If got data
           if (FLAGC == 1) begin
              state <= state + 1;
              // assert SLOE
              SLOE_R <= 0;
           end
           // or stick here to wait for data
        end
        // Wait 2 IFCLK before we assert SLRD

        4: begin
           if (RW == 0 && FLAGC == 1) begin
              if (fr_or_sec == 0) begin
                 data[255:16] <= data[239:0];
                 data[15:0] <= FD;
                 SLOE_R <= 1;
                 SLRD_R <= 1;
                 fr_or_sec <= 1;
              end else begin
                 data[15:0] <= FD;
                 count <= count + 1;
                 SLRD_R <= 0;
                 SLOE_R <= 0;
                 if (count == 15) begin
                    state <= state + 1;
                 end
                 fr_or_sec <= 0;
              end
           end else begin
              SLOE_R <= 1;
              SLRD_R <= 1;
           end
        end

        5: begin
           // Reset SLRD and SLOE
           SLRD_R <= 1;
           SLOE_R <= 1;
           state <= state + 1;
           count <= 0;
        end

        6: begin
           // Do work here
           // data_out <= 256'hd1310ba698dfb5ac2ffd72dbd01adfb7b8e1afed6a267e96ba7c9045f12c7f99;
           // data_out <= 256'h3400111122223333444455556666777788889999aaaabbbbccccddddeeeeffff;
           data_out <= data;
           count <= 0;
           state <= state + 1;
        end

        7: begin
           // Select fpga->host EP
           FD_reg_connected <= 1;
           FIFOADR1_R <= 0;
           count <= 0;
           state <= state + 1;
        end
        // Skip 1 tick to stabilize FIFOADR1_R

        9: begin
           // If got room
           if (FLAGB == 1) begin
              FD_R <= data_out[255:240];
              data_out[255:16] <= data_out[239:0];
              count <= count + 1;
              SLWR_R <= 0;
              if (count == 15) begin
                 state <= state + 1;
                 PKTEND_R <= 0;
              end else begin
                 PKTEND_R <= 1;
              end
           end else begin
              SLWR_R <= 1;
           end
        end

        10: begin
           // Reset SLWR
           SLWR_R <= 1;
           PKTEND_R <= 1;
           // Back to reading
           state <= 0;
        end

        default:
          state <= state + 1;

      endcase

   end

end

endmodule