Follow @Openwall on Twitter for new release announcements and other news
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Sun, 10 Nov 2013 09:45:51 +0400
From: Solar Designer <solar@...nwall.com>
To: john-dev@...ts.openwall.com
Subject: Re: ZedBoard: bcrypt

On Wed, Nov 06, 2013 at 12:45:28PM +0100, Katja Malvoni wrote:
> I was thinking about putting code which does loads and stores to shared
> BRAM in arbiter so it's implemented only once and not once per core. But
> this would add additional delay cycle to RAM which holds S-boxes. In this
> case, total delay would be 3 cycles so 3 instances per core would be
> necessary.

This may be fine.  I don't see why it takes an extra cycle rather than
uses up a port, though.

> > BTW, I think we have a carry chain across cells, on LUTs outputs.
> > Is it being used for Blowfish's 32-bit addition?
[...]

> I think it is being used. Attached table contains additions and xors for L
> and R calculation. And image is screenshot of one of additions placed in
> MUXCY cell which is part of CARRY4.

Thanks!

Alexander

Powered by blists - more mailing lists

Confused about mailing lists and their use? Read about mailing lists on Wikipedia and check out these guidelines on proper formatting of your messages.