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Date: Wed, 6 Nov 2013 12:45:28 +0100
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: ZedBoard: bcrypt

On Tue, Nov 5, 2013 at 11:22 PM, Solar Designer <solar@...nwall.com> wrote:

> Hi Katja,
>
> On Tue, Nov 05, 2013 at 05:21:10PM +0100, Katja Malvoni wrote:
> > On Sun, Nov 3, 2013 at 11:02 PM, Solar Designer <solar@...nwall.com>
> wrote:
> >
> > > Great!  I think your next step is to implement two instances of bcrypt
> > > per core, so that there are no wait-only cycles.
> [...]
>
> > I have implementation which works in simulation but not on the board.
> > However, utilization is:
> >
> > Register: 5%
> > LUT: 41%
> > Slice: 66%
> > RAMB36E1: 6%
> > RAMB18E1: 1%
> > BUFG: 3%
> > With these numbers there is no point in trying to find bug(s).
> > I'll try to redesign current implementation.
>
> Are these numbers for one core (two instances of bcrypt)?  Ouch.
>

Yes, that is correct. I tried to reduce initialization code but it didn't
help much - LUT: 39%, Slice: 63%
I was thinking about putting code which does loads and stores to shared
BRAM in arbiter so it's implemented only once and not once per core. But
this would add additional delay cycle to RAM which holds S-boxes. In this
case, total delay would be 3 cycles so 3 instances per core would be
necessary.


> BTW, I think we have a carry chain across cells, on LUTs outputs.
> Is it being used for Blowfish's 32-bit addition?  How can we make sure
> it's used?  I had essentially this same question here:
>
> http://www.openwall.com/lists/crypt-dev/2011/06/27/3
>
> Also found:
>
> http://www.openwall.com/lists/crypt-dev/2011/06/09/1
>


I think it is being used. Attached table contains additions and xors for L
and R calculation. And image is screenshot of one of additions placed in
MUXCY cell which is part of CARRY4.

Katja

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