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Date: Sat, 20 Sep 2014 15:36:08 +0400
From: Solar Designer <solar@...nwall.com>
To: john-users@...ts.openwall.com
Subject: Re: Parallella benchmarks?
On Fri, Sep 19, 2014 at 08:42:56PM -0800, Royce Williams wrote:
> My real motivation was looking around for the best way to do descrypt
> on readily available FPGAs with JtR. Parallella would also be
> attractive if the price/performance was on par with the
> ztex-bruteforcer work (960Mh/s at 40W), or at least significantly
> ahead of GPU.
The quad-FPGA ZTEX 1.15y has about 8x more FPGA fabric than Parallella
with Zynq 7020 does (and ~25x more than Parallella with Zynq 7010 does),
yet costs about the same as Parallella with Zynq 7020 (if you're OK
buying used ZTEX boards on eBay or similar; otherwise, it's ~2x more for
new boards). Additionally, ZTEX boards have been extensively tested
with Bitcoin mining, so they should not experience the voltage drop and
insufficient decoupling and cooling problems that are seen with ZedBoard
and Parallella. So obviously ZTEX wins for this application, except
that it's not usable along with JtR yet - we need to work on that.
> In my ideal world, I'd like to chip in with others to sponsor JtR work
> on what might be called descrypt-ztex or descrypt-parallella. I'm
> just a solo researcher on this one, but since there looks like a lot
> of potential, I could chip in more than lunch money. :-)
This might help. Please be more specific (off-list is OK).
We readily have some ZTEX 1.15y boards within our team, but we have
difficulty dedicating anyone's time to the effort.
> The obvious problem is that most folks aren't super-interested in
> descrypt. It does seem to make a good first port to a new platform,
> so it will almost certainly happen, but it's not likely to inspire a
> Kickstarter, etc.
Yeah, probably not a Kickstarter thing.
I think we need bcrypt and descrypt on ZTEX. For bcrypt, it's OK to
have JtR generate candidate passwords as usual (but we'd need async
communication). For descrypt, we'd need to be generating portions of
candidate passwords on FPGAs (luckily, recent changes to JtR's formats
API allow for that).
Alexander
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