[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Sat, 1 Sep 2012 03:59:32 +0400
From: Solar Designer <solar@...nwall.com>
To: john-users@...ts.openwall.com
Subject: Re: Questions about compiling for Optimal CPU Performance
On Wed, Aug 29, 2012 at 08:27:21AM -0400, Brad Tilley wrote:
> My older Intel Celeron CPU lists sse, sse2 and sse3 as supported in
> /proc/cpuinfo, should I make-x86-sse2 or make-x86-native when compiling
> jumbo-6? Or does the difference really matter?
In your case, this should make no difference. SSE3 is not being used
anyway. The newer SSSE3 (different from plain SSE3) is being used when
you build with linux-x86-native on a system that has SSSE3, for a speedup
of maybe 1% or less at some hashes (and you don't seem to have SSSE3
anyway). You'd get greater speedup (a few percent at some hash types)
by using linux-x86-sse2i instead (icc-precompiled SSE2 code for the
sse-intrinsics.c source file).
SSE4.1, AVX, XOP are used by -native when available, but you don't seem
to have SSE4.1 and you definitely don't have AVX and XOP. SSE4.1 is
only used in the raw-sha1-ng format.
> Also, the Makefile has two possibilities for OpenMP...
>
> 1. -fopenmp
This one is for use on most systems other than 32-bit x86.
> 2. -fopenmp -msse2
This one is for use on 32-bit x86 with at least SSE2 (like yours).
> Which one should be uncommented for optimal performance when the CPU lists
> multiple sse implementations. For example, should a CPU support sse4,
> would I be limiting performance if I opted for OpenMP with -msse2, or not?
When you specify -msse2, you don't disable anything - you merely let the
compiler use SSE2 and you have it define __SSE2__, so that the source
files know they may use SSE2 intrinsics. If building with -native made
sense for your CPU, which apparently it does not, then you could be
doing so along with having enabled -msse2 above - it would not hurt
(it'd be a no-op, though, because -native would imply -msse2 and more).
Building with OpenMP on a 32-bit Celeron probably doesn't make sense,
though. According to this table:
http://en.wikipedia.org/wiki/List_of_Intel_Celeron_microprocessors
all 32-bit Celerons are single-core.
> Just curious, perhaps this is documented someplace on the wiki and I
> missed it.
Actually, maybe it is not. Perhaps we need to add a comment to this
place in the Makefile.
Thanks,
Alexander
Powered by blists - more mailing lists
Confused about mailing lists and their use?
Read about mailing lists on Wikipedia
and check out these
guidelines on proper formatting of your messages.
