Date: Sun, 19 Oct 2008 17:27:06 +0900 From: "Project: NANIYA" <geek4civic@...il.com> To: john-users@...ts.openwall.com Subject: Re: Breaking UNIX crypt() on the PlayStation 3 Alexander, Konnichiwa. 1st post here for me. 2008/10/17 Solar Designer <solar@...nwall.com>: > Isn't the PPU capable of issuing more instructions per cycle (than the > SPUs)? If not more AltiVec instructions, then maybe more PowerPC > instructions intermixed with AltiVec ones? BTW, this additional > optimization - using native 64-bit instructions intermixed with vector > ones - might work on all of: SSE2, AltiVec, SPU. Intemixing VMX and ALU has a problem. VMX load and store always spend 1 or 2 GPRs, and they have no "constant displacement" addressings. eg) LVX V7,R0,R1 # load from (R0+R1), when R0 is always 0 VMX does not have "load from nnn(Rn)." Thus, VMX sequences make pressure to GPR or ALU OP. And now, we have achieved more efficient sequences on SPU (and PPU VMX :)) it is harder to interleave 64-bit GPR sequences into (shorter) VMX sequences. I think it would be better for PPU to let run simulataneously with two threads, VMX and ALU. But still I have interests to the former strategy. Btw, do you need faster implementation of DES? (on x86, x64 and other chips) -- NAKAMURA, Takumi -- To unsubscribe, e-mail john-users-unsubscribe@...ts.openwall.com and reply to the automated confirmation request that will be sent to you.
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