Openwall GNU/*/Linux - a small security-enhanced Linux distro for servers
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Wed, 21 Dec 2005 20:57:09 +0100
From: Simon Marechal <>
Subject: Re:  john improvement suggestions

Solar Designer wrote:
> On some CPUs, ALU+SSE, MMX+SSE, and even ALU+MMX+SSE could be beneficial,
> too - and people have been doing that.  There's definitely room for
> improvement here.

MMX and SSE are the same physical registers (with FPU too) on my athlon 
xp, and AFAIK, this is true for the other architectures too:

	mov $0x4444, %eax
	movd %eax, %mm0
	pxor %xmm0, %xmm0
	movd %eax, %mm1
	paddd %mm1, %mm0
	movd %mm0, %eax

eax will have the value 0x4444
if the "pxor %xmm0, %xmm0" line is removed, it will be 0x8888

I do not think it is possible to use at the same time MMX+SSE effectivly.

The main problem with using ALU+(MMX/SSE) is that x86 processors are 
register starved.

However there is definitly room for improvement on amd64.

Download attachment "smime.p7s" of type "application/x-pkcs7-signature" (2525 bytes)

Powered by blists - more mailing lists

Your e-mail address:

Powered by Openwall GNU/*/Linux - Powered by OpenVZ