[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Mon, 27 Apr 2015 07:45:32 +0300
From: Solar Designer <solar@...nwall.com>
To: john-dev@...ts.openwall.com
Subject: Re: [GSoC] JtR SIMD support enhancements
On Mon, Apr 27, 2015 at 06:12:25AM +0300, Solar Designer wrote:
> https://software.intel.com/en-us/articles/intel-xeon-phi-core-micro-architecture
>
> "Many changes were made to the original 32-bit P54c architecture to make
> it into an Intel Xeon Phi 64-bit processor."
>
> BTW, this article on the microarchitecture describes several differences
> relative to Pentium that may be useful to us, including on possibly
> optimizing our bcrypt code to run better on Xeon Phi's scalar units -
> but we'll probably have to do that in assembler. Extrapolating from
> Pentium 120 MHz 20.4 c/s for hand-tuned asm:
>
> 20.4 * 60*1.053 / 0.12 = 10740 c/s
>
> Our current speed is twice worse:
>
> 10740/5339 = 2.01
This should have been:
10740/6339 = 1.69
So our current speed is not that bad, but likely it can still be
improved by up to 70%.
Alexander
Powered by blists - more mailing lists
Confused about mailing lists and their use?
Read about mailing lists on Wikipedia
and check out these
guidelines on proper formatting of your messages.
