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Date: Sun, 8 Sep 2013 10:15:57 +0200
From: Katja Malvoni <>
Subject: Re: ZedBoard / Parallella: bcrypt

Hi Alexander,

On Sun, Sep 8, 2013 at 12:42 AM, Solar Designer <> wrote:

> Also, to remind you, we already had Yuri's bcrypt on FPGA working
> correctly (including on the actual Spartan-6 device) - so maybe you
> could have started with his code - or you may use it as a reference.
> I am fine with you starting from scratch, though.

I started from scratch because I had problems understanding that code and I
knew I'll have to make changes in order to use it on Zedboard so it was
easier for me to start from scratch and to work with code I understand.

> 3 cycles is a lot.  IIRC, it was 1 cycle on Spartan-6 and Virtex-6 when
> we experimented with bcrypt on those, and it could be 2 cycles with
> buffer registers if we wanted those (presumably for a higher clock rate).
> Is Zynq worse in that aspect?

Xilinx tools offers two types of block RAM to be used, one is native and
another one is with AXI4 interface. I need bram with AXI4 because I use
that bram to communicate with PS. I think that native bram has 1 cycles
latency, I'm not sure.
Another option is having inferred native dual port bram and copying
everything from bram used to communicate with PS to internal bram. This
will save time but it will have impact on area.

Yes, when you mentioned having used a port to do DMA a while ago, this
> felt wasteful to me - and now you confirm that it is.  Perhaps you
> should reconsider that?  With DMA, you may be making data transfers
> from/to host slightly faster, but you're probably almost halving the
> computation speed by wasting half the block RAM ports.

The problem is that I don't know how else to communicate with PL. There is
no reference from Xilinx and connecting my logic to other RAM port was the
only way I could access data sent from host. Another way would be to make
second bram port external and than to connect it to user logic but still it
would use only one port. It took me a lot of time to figure out how to do
that communication and I really don't have any other idea except this one.

> Is it by any chance possible to use the same block RAM ports for both
> DMA and PL access, at different times?

This is not possible, I can connect only one thing on one port. Bram is not
connected directly to bus, it's connected to bram controller (I added bram
controller interface on my logic) so I can't share it with DMA.



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